1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular to a method for forming a bit line contact and a storage electrode contact for a high integration device, without damaging a device isolating insulating film and a substrate.
2. Description of the Background Art
Recently, the high integration of a semiconductor device has been remarkably influenced by the development of techniques for forming a fine pattern. In a method for fabricating the semiconductor device, it is essential to miniaturize a photoresist film pattern used as a mask in an etching or ion implantation process.
Resolution (R) of the photoresist film pattern is proportional to a light source wavelength (.lambda.) and a process variable (k) of a micro exposure device, and inversely proportional to a numerical aperture (NA) of the exposure device. EQU R=k*.lambda./NA
Here, in order to improve optical resolution of the micro exposure device, the wavelength of the light source is decreased. For example, resolution of the G-line and I-line micro exposure devices, having wavelengths of 436 nm and 365 nm, respectively, is about 0.7 .mu.m and 0.5 .mu.m, respectively. Accordingly, the exposure device using a deep ultraviolet (DUV) light having a small wavelength, for example, a KrF laser of 248 nm or an ArF laser of 193 nm, is employed to form a fine pattern below 0.5 .mu.m. In addition, in order to improve the resolution, a method for using a phase shift mask as a photo mask has been suggested. A contrast enhancement layer (CEL) method for forming a thin film on a wafer has been suggested for enhancing an image contrast. A tri layer resist (TLR) method has been suggested for positioning an intermediate layer, such as a spin on glass (SOG) film between two photoresist films. And a silylation method has been suggested for selectively implanting a silicon into an upper portion of a photoresist film.
According to the high integration of the semiconductor device, a size of a contact hole, which connects the upper and lower conductive interconnections, and a space between the contact hole and an adjacent interconnection are decreased, and an aspect ratio of the contact hole is increased.
Thus, the high integration semiconductor device having multi-layer conductive interconnections requires precise mask alignment in a contact formation process, thereby reducing a process margin.
In order to maintain a space between the contact holes, masks are formed in consideration: of misalignment tolerance in a mask alignment, lens distortion in an exposure process, critical dimension variations in mask formation and photoetching processes, and mask registration.
In addition, there has been taught a self aligned contact (SAC) method for forming a contact hole according to a self alignment method to overcome a disadvantage of a lithography process.
The SAC method may use a polycrystalline silicon layer, a nitride film or an oxide nitride film as an etching barrier film. In general, the nitride film is employed as the etching barrier film.
Although not illustrated, the conventional SAC method for fabricating the semiconductor device will now be described.
Firstly, a substructure consisting of, for example, a device isolating insulating film, a gate insulating film and a metal-oxide semiconductor field effect transistor (MOSFET) having a gate electrode overlapped with a mask oxide film pattern, and source/drain regions are formed on a semiconductor substrate. An etching barrier film and an interlayer insulating film consisting of an oxide film are sequentially formed over the entire structure.
Thereafter, a photoresist film pattern is formed to expose the interlayer insulating film in a presumed region of a storage electrode contact or bit line contact on the semiconductor substrate.
The interlayer insulating film exposed by the photoresist film pattern is dry-etched to expose the etching barrier film. Then, a contact hole is formed by etching the etching barrier film.
In the conventional SAC method for fabricating the semiconductor device, when the bit line contact and the storage electrode contact for a device below 0.15 .mu.m are formed, a general circular contact cannot obtain a contact region due to misalignment in the lithography. In order to overcome such a disadvantage, there has been taught a method for forming a conductive layer by etching the oxide film by using the photoresist film pattern for exposing the contact region in a T or I type as an etching mask, and forming a plug by chemical mechanical polishing (CMP) the conductive layer.
The T type mask has a sufficient misalignment margin of the bit line contact. However, the contact hole has a sloped section in the storage electrode contact formation region due to misalignment and the contact oxide film etching process, and thus the contact region is difficult to obtain. Accordingly, this method cannot be applied to a device below 0.13 .mu.m.
In addition, the I type mask etches the oxide film by shifting a device isolating mask on the device isolating insulating film. Here, an etching area is wider than a mask area, and thus a high selection ratio for a nitride film is hardly obtained.
The etching area has to be much smaller than the non-etching area in order to obtain the high selection ratio for the nitride film in the oxide film etching process. When the etching area is wider than the non-etching area, a polymer cannot sufficiently protect the nitride film.
Moreover, since the etching process using the T type mask or I type mask is performed in the active region of the semiconductor substrate, the active region is exposed to the plasma and damaged in the oxide film etching process, and thus increases a resistance of the contact and a current leakage.